The active matrix type LCD employing a thin film transistor having a number of pixels, has a thin and light device size and displays excellent picture quality comparable to the Cathode Ray Tube device.
FIG. 1 is a cross-sectional view showing a general TFT-LCD. As shown in the drawing, gate bus lines 12 are disposed on an array substrate 10 with a regular distance. Data bus lines 14 are disposed on the array substrate 10 to be disposed perpendicular to the gate bus lines 12 thereby defining pixels. A thin film transistor 15 is disposed at each intersection region of the gate bus line 12 and the data bus line 14. At this time, the thin film transistor 15 comprises a gate electrode 12a being extended from the gate bus line 12 toward the pixel region; a channel layer 16 being disposed over the gate electrode; a source electrode 14a being extended from the data bus line 14 to overlap one side of the channel layer 16; a drain electrode 14b to overlap the other side of the channel layer 16. A pixel electrode 18 is formed at each pixel region to be contacted with the drain electrode 14b of the thin film transistor.
Herein, the gate bus line 12, the data bus line 14, the channel layer 16 and the pixel electrode 18 are formed according to the photolithography process that is performed by coating a resist, developing and exposing the resist.
However, the mask used in the exposing step has a relatively small size compared to the dimension the array of substrate. Accordingly, the array substrate is divided into a selected number of pieces and the array substrate is exposed partially so as to form one type of pattern on the array substrate.
That is, as shown in FIG. 2, the array substrate 10 is divided into, for example, six pieces. Then, a mask(not shown) for forming pattern is arranged in a region a1 and exposed. Next, the mask moves to the respective regions a2,a3,a4,a5,a6 to perform exposing steps. Herein, the respective regions a1.about.a6 are called as "shots".
However, following problems are incurred due to the partial exposing step.
For example, when the masks are arranged for defining the data bus lines, there may be occurred misalignment, and the overlapping degree between the gate electrode 12a and the source electrode 14a is different from the respective shots a1.about.a6.
Accordingly, the values of parasitic capacitance Cgs(hereinafter "gate-source capacitance") of the respective shots are different from each other thereby changing pixel voltage variation(hereinafter "kick-back voltage") that relates to the picture quality of LCD device. Therefore, the picture quality of each shot is different and stains are occurred in the screen.
More particularly, the kick-back voltage can be understood with reference to following equation 1. ##EQU1##
wherein, .DELTA. Vp means the kick-back voltage,
Cgs means the parasitic capacitance between the gate electrode and the pixel electrode, PA1 Clc means a liquid crystal capacitance in the unit pixel, PA1 Cst means a storage capacitance in the unit pixel, PA1 Vgh means an ON voltage in the gate bus line, and PA1 Vbl means an OFF voltage in the gate bus line. PA1 an array substrate; PA1 a gate bus line disposed on the array substrate in a selected direction; PA1 a data bus line disposed to be crossed with the gate bus line; PA1 a pair of thin film transistors disposed at an intersection of the gate bus line and the data bus line and disposed at both sides of the data bus line respectively; PA1 a pixel electrode in contact with the respective thin film transistors; PA1 a gate insulating layer for insulating the gate bus line and the data bus line; and PA1 an intermetal insulating layer for insulating the data bus line and the pixel electrode, PA1 wherein, the pair of thin film transistors have a source electrode in common. PA1 an array substrate; PA1 a gate bus line disposed on the array substrate in a selected direction; PA1 a data bus line disposed to be crossed with the gate bus line; PA1 a pair of thin film transistors disposed at an intersection of the gate bus line and the data bus line and disposed at both sides of the data bus line respectively; PA1 a pixel electrode in contact with the respective thin film transistors; PA1 a gate insulating layer for insulating the gate bus line and the data bus line; and PA1 an intermetal insulating layer for insulating the data bus line and the pixel electrode; PA1 wherein the thin film transistors comprise a first gate electrode and a second gate electrode being extended from both sides of the gate bus line with respect to the data bus line; a first channel layer and a second channel layer disposed at the first gate electrode and the second gate electrode respectively; a common source electrode being extended from the data bus line to be overlapped with one sides of the first and second channel layers; and drain electrodes overlapped with the other sides of the first and second channel layers and contacted with the pixel electrode.
According to equation 1, the kick-back voltage .DELTA. Vpis a function of the gate-source capacitance Cgs. When the capacitance Cgs is different in the respective shots, the kick-back voltage .DELTA. Vp is also different in the respective shots and quality difference is occurred.